Highly Integrated CMOS Interface Circuits for SiPM Based PET Imaging Systems
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Recent developments in the area of Positron Emission Tomography (PET) detectors using Silicon Photomultipliers (SiPMs) have demonstrated the feasibility of higher resolution PET scanners due to a significant reduction in the detector form factor. However, reduced size implies a corresponding increase in the detector density, resulting in a proportional rise in the number of channels interfacing a SiPM array with the digital backend. This thesis explores a row-column-diagonal decoding architecture to simplify and reduce the required channels between the individual elements in the SiPM array, and the backend digital electronics. The front-end interface is designed using a current amplifier with a very low input impedance. Accumulation of noise presents itself as a challenge to the row-column summation architecture. This may lead to an increased chance of false triggering as compared to a more traditional approach using dedicated single-channel readout for each individual SiPM device. This work uses a current comparator topology to act as a thresholding circuit to minimize the accumulation of `dark noise' and reduce the possibility of a false triggering event. A separate high-speed timing channel is designed to acquire the timing information across all the channels. Line drivers are used to interface this chip to a wide variety of impedances, allowing a general purpose interface to the digital backend. The proposed readout electronics has been realized in STMicroelectronics 130 nm CMOS process.
- Electrical engineering