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dc.contributor.authorAzadeh, Mohammaden_US
dc.date.accessioned2009-10-06T00:22:11Z
dc.date.available2009-10-06T00:22:11Z
dc.date.issued2000en_US
dc.identifier.otherb45424172en_US
dc.identifier.other46914957en_US
dc.identifier.otherThesis 49827en_US
dc.identifier.urihttp://hdl.handle.net/1773/6104
dc.descriptionThesis (Ph. D.)--University of Washington, 2000en_US
dc.description.abstractThe combination of optoelectronic arrays consisting of optical emitters and detectors with processing electronics constitutes the basis of smart pixel arrays. These architectures present an attractive basis for optoelectronic systems. Ideally, they combine the efficiency of electronic circuits with the interconnection capabilities of optics to achieve improved performance or implement new functionalities. This dissertation deals with optoelectronic interconnections in general, and with the important special case of optoelectronic feedback. Such systems, whether integrated or distributed, open up a variety of new prospects for optoelectronic systems, especially in sensor applications. These concepts are first developed for a single pixel, and then generalized to in a matrix formalism for an arbitrary smart pixel array. An important part of a smart pixel array is the electronic circuits required to interface the optoelectronic devices and to perform the necessary signal processing tasks. A new approach based on a current mode processing architecture is presented and implemented in CMOS technology as an ASIC integrated circuit. Experimental results from two fabricated CMOS chips as well as LED and VCSEL-based optoelectronic arrays are presented.en_US
dc.format.extentviii, 132 p.en_US
dc.language.isoen_USen_US
dc.rightsCopyright is held by the individual authors.en_US
dc.rights.urien_US
dc.subject.otherTheses--Electrical engineeringen_US
dc.titleCurrent mode processing and architecture for optoelectronically interconnected arraysen_US
dc.typeThesisen_US


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