Taylor, MichaelVijaya Ranga, Shashank2021-08-262021-08-262021-08-262021VijayaRanga_washington_0250O_23010.pdfhttp://hdl.handle.net/1773/47277Thesis (Master's)--University of Washington, 2021Hardware accelerators are an active field of research in computer architecture as one solution to overcome hurdles such as dark silicon. A host processor interfaces with an accelerator and offloads the time-consuming computations onto it. BlackParrot is one such accelerator host being developed at the Bespoke Silicon Group. The initial performance comparisons of BlackParrot with other similar RISC-V processors are promising, and it is validated in silicon through a tapeout in 12 nm technology. BlackParrot is currently an industrial-strength ASIC Design, but ASIC flows are not readily available to individual users outside research groups that want to use BlackParrot in their designs. Open-source ASIC flows mitigate this to a certain extent, but taping out a chip is a costly exercise. An alternative to ASIC design is to use simulation only to validate the design, but this does not provide silicon validation and is an issue for long-running benchmarks which could run for days. In order to provide users with a silicon option for their designs using BlackParrot, the most viable option is an FPGA system. FPGAs allow rapid design iterations and provide an opportunity to prototype the system in real hardware. This thesis examines two tracks of building out BlackParrot's FPGA environment: i) by integrating BlackParrot into the OpenPiton memory system and validating it on an FPGA, and ii) by creating an in-house system using the Zynq-7000 SoC available on specific FPGAs and supporting hardware cosimulation for the BlackParrot design.application/pdfen-USCC BYBlackParrotFPGAOpenPitonProcessorRISC-VComputer engineeringElectrical engineeringThesis