2026-09-18T17:56:03Zhttps://digital.lib.washington.edu/server/oai/request

oai:digital.lib.washington.edu:1773/338112026-02-15T22:39:33Zcom_1773_4888col_1773_4915

Rudell, Jacques C Pepin, Eric Philip 2015-09-29T18:02:25Z 2015-09-29 2015 Pepin_washington_0250O_15045.pdf http://hdl.handle.net/1773/33811 Thesis (Master's)--University of Washington, 2015 This work explores the challenges of implementing practical, electrical neural stimulation interfaces using modern silicon CMOS technologies. To overcome said challenges, which stem from the discrepancy between the low-voltage limitations of modern CMOS devices and the large stimulation voltages often observed at response-evoking stimulus levels, a new stimulator front-end is proposed. The high-voltage compliant front-end can reliably drive biphasic, constant-current stimulus through a wide range of electrode impedances while being safely implemented in a low-voltage, bulk-CMOS technology. The topology of the front-end is based on a sink-regulated H-bridge. Stimulus current is supplied using specialized, fully-integrated dynamic voltage supplies (DVSs), which are controlled in closed-loop to have an output voltage approximately equal to the voltage of the electrode each supplies stimulus to. The entire stimulus waveform is regulated by a single, low-voltage current-DAC, which can safely interface with the electrodes (which may be at high voltages) via specialized high-voltage adapter (HVA) circuits. To account for “capacitive-looking” electrodes and to provide unique, “electrode-invariant” performance, the front-end uses the balancing stimulus current to discharge the electrode-tissue-interface impedance (ZE), and only after full ZE discharge has been detected is a DVS used to supply the remaining balancing stimulus. In this thesis the described front-end topology and the enabling high-voltage operating circuits are presented and discussed in detail. Additionally, a stand-alone DVS circuit has been fabricated in 65nm bulk-CMOS, demonstrating the power-supplying and transient performance required by the proposed stimulator design. Another chip, featuring the entire integrated neural stimulator front-end, has also been designed in 65nm bulk-CMOS, with post-layout simulations showing ±11V compliance (approximately) across a 50μA to 2mA stimulus amplitude range. The efficacy of the proposed integrated electronics in potential neural stimulation applications is also explored using a board-level prototype and in-vivo evaluation. application/pdf en_US Copyright is held by the individual authors. high-voltage; low-voltage CMOS; neural stimulation Electrical engineering electrical engineering High-Voltage Compliant, Electrode-Invariant Neural Stimulation Electronics Compatible with Low-Voltage, Bulk-CMOS Integration Thesis Restrict to UW for 1 year -- then make Open Access 2016-09-28T18:02:25Z open.access