Integrated Circuit Design Techniques for Full-Duplex Radios in CMOS: Broadband Self-Interference Cancellation and Oversampling Feedforward Phase Noise Suppression

Abstract

The rapid expansion of wireless systems in applications such as autonomous platforms, smart infrastructure, industrial Internet of Things (IoT), and immersive communications continues to drive the demand for higher data rates under stringent constraints on power consumption, hardware complexity, and spectral resources. As fifth-generation (5G) networks mature and sixth-generation (6G) technologies emerge, the increasing congestion of the wireless spectrum has made improving spectral efficiency a central challenge in modern transceiver design. In-band full-duplex (FD) communication has gained significant attention as a means to enhance spectral efficiency by enabling simultaneous transmission and reception over the same frequency channel. However, its practical realization is fundamentally limited by self-interference (SI), where the strong transmit signal leaks into the receiver and severelydegrades sensitivity and linearity. This dissertation presents integrated circuit techniques in CMOS to address SI and its associated system-level limitations in FD radios. To address RF-domain SI under dynamic channel conditions, a highly tunable RF selfinterference canceler is first developed based on a multi-tap complex finite impulse response (FIR) architecture with programmable delay and enhanced linearity. The canceler achieves up to 30 dB SI suppression over a 40 MHz bandwidth in real wireless environments, with an input-referred IIP3 of +38 dBm. When combined with a machine-learning-assisted adaptation loop, the system achieves convergence times on the order of 10 ms, enabling rapid tracking of time-varying interference. Building upon RF cancellation, a 2.4 GHz full-duplex (FD) transceiver is presented to achieve wideband and long-delay SI suppression in practical multipath environments. The proposed architecture integrates an electrical-balanced duplexer (EBD), broadband RF FIR cancelers, and a digital-assisted baseband cancellation path capable of mitigating delay spreads up to 174 ns. Fabricated in a 40 nm CMOS process, the transceiver achieves 62 dB SI suppression over a 120 MHz bandwidth for short delay spreads and maintains 23 dB cancellation across the same bandwidth for long-delay conditions. The RF cancellation path achieves an input-referred IIP3 of +42 dBm, while the receiver exhibits a noise figure of 6.8 dB. Despite these advances in RF and baseband SI cancellation, the achievable performance is ultimately constrained by phase noise from the local oscillator. Phase noise introduces random phase mismatch between the SI signal and its reconstructed replica, resulting in residual interference that limits cancellation depth, particularly in high interference-to-noise ratio conditions. This limitation becomes critical in wideband FD systems and motivates the need for improved frequency synthesis. To address this challenge, an oversampling feedforward phase-noise cancellation (OSFFPNC) technique is proposed to improve the performance of phase-locked loops (PLLs). By introducing an auxiliary feedforward path, the proposed architecture extends the effective suppression bandwidth of voltage-controlled oscillator (VCO) phase noise toward the reference frequency without degrading in-band noise performance or loop stability. A 5 GHz PLL prototype fabricated in a 28 nm CMOS process achieves an RMS jitter of 198.5 fs and a normalized jitter-power figure-of-merit (FoMN) of −267.05 dB. Collectively, the techniques presented in this dissertation establish a systematic approach to mitigating self-interference and its fundamental limitations in full-duplex radios. By progressively addressing RF cancellation, wideband and long-delay interference, and phase noise constraints, this work enables more practical and scalable implementations of next-generation spectrally efficient wireless transceivers.