Integrated Wideband Self-Interference Cancellation Techniques for FDD and Full-Duplex Wireless Communication

Abstract

The continued demand for higher levels of wireless access and increased data rates for a variety of applications from mobile smart phones to back haul point-to-point communication, continues to drive research that enables new spectrum opportunities, reduces form factor and lowers the cost of hardware solutions. The current RF spectrum, which is often referred to as the frequency band from 1-6GHz, has become increasingly crowded with only a limited amount of unused and unlicensed spectrum. This dissertation explores and implements, single-chip hardware front-end solutions which the specific aim to increase data rates for each single-user using two techniques: a. Using In-band full-duplex radio techniques with self-interference cancellation; b. High-speed communication using large bandwidths available at mmWave frequencies. The advantages, challenges and achievements associated with the two proposed techniques will be described in the following paragraphs. First, in-band full-duplex communication potentially increases spectral efficiency within existing RF standards. This will allow the combination of dedicated transmitting and receiving bands into a single band which would more than double the spectral efficiency. However, this leads to an extremely challenging problem associated with transmitter self-interference cancellation. To date, two full-duplex chips have been designed, fabricated and tested, each with a self-interference cancellation function. The first IC is an analog full-duplex front-end for Bluetooth (BLE) applications. Inside the proposed chip, a self-interference cancellation (SIC) circuitry, a low-power receiver, combined with a harmonic-rejection power amplifier (HRPA) are implemented to reduce the transmitter-to-receiver self-interference, and enable full-duplex operation. These techniques were applied towards the realization of a prototype silicon device which implements a tunable self-interference mitigation canceller function with a current-mode LNA and passive-mixer based front-end, and a power amplifier topology to reduce out-of-band emissions. This chip was fabricated in 40nm 6-metal stack CMOS process to achieve more than 30dB measured self-interference cancellation over 4MHz bandwidth, and an integrated power amplifier (PA) which suppresses the 3rd and 5th harmonics by 30dB and 15dB, respectively. The PA delivers a maximum output power of +14dBm with a drain efficiency of 33%. The self-interference cancellation circuitry utilizes an active area of 131×112.5 µm2, has a power consumption of 0.25mW, and degrades the receiver noise figure (NF) by less than 0.6dB. The second IC is a transceiver front-end, which includes a dual-injection path self-interference (SI) cancellation circuitry to enable wideband full-duplex communication with a high-power transmitter. The proposed SI cancellation circuitry is implemented using: (1) one feedforward cancellation path containing a 5-tap analog adaptive filter (AF) between the transmitter (TX) output and the receiver (RX) input; (2) a second cancellation path containing a 14-tap low-frequency AF with a point of injection at the RX baseband output; (3) a phase noise cancellation method which reduces the phase noise (PN) associated with the down-conversion in the BB cancellation path for the TX SI signal; (4) an integrated noise canceling power amplifier (PA). A prototype 40nm TSMC device was fabricated which demonstrates more than 50dB SI cancellation over 42MHz bandwidth and a 10dB attenuation of TX SI PN in the RX signal path. The two cancelling filters dissipates 11.5mW, with a measured P-1dB and IIP3 of 27/26.5dBm and 36/34.5dBm, respectively. The RX noise figure is degraded by less than 1.55dB when both cancelers are enabled. The PA has a measured output of P-1dB/Psat of 25.1/26.5dBm, respectively. The total chip die area is 3.5 mm2 with an overall transceiver power consumption of 49mW excluding the integrated power amplifier. Second, although the lower frequency RF band appears saturated, the vast available spectrum at mmWave frequencies (30 – 300 GHz) presents a potentially attractive solution for high-speed communication. However, communication at mmWave frequencies brings up many new challenging problems for designers when attempting to realize a wideband high accuracy wideband quadrature generator is one of them. One mmWave IC, which includes an integrated two-stage polyphase filter (PPF) with feedback control, is proposed for quadrature local oscillator (LO) generation at millimeter-wave frequencies. To minimize the in-phase (I) and quadrature (Q) mismatch, the second stage of the PPF utilizes triode-region NMOS transistors to implement variable resistors where the resistance is precisely controlled by modulating the shared gate-to-source bias voltage at the gate of NMOS devices. The gate bias voltage of the triode region devices is set by a feedback loop and changes according with variations in process, voltage, and temperature (PVT). A prototype quadrature signal generator, employing this PPF design, is integrated in 28nm LP CMOS process. A worst-case measured phase/amplitude imbalance of 2°/ 0.32dB (TT dies) and 2.2°/ 0.55dB (SS dies) is reported over 7GHz bandwidth for a fixed control current (ICtrl). By retuning ICtrl every 7GHz, this IQ generator would maintain the measured quadrature accuracy from 55-to-70 GHz. The core area occupied by the IQ generator circuitry is 20µm × 40µm and the device consumes less than 192µW, of which 120/72 µW comes from the feedback control-loop / Opamp, respectively. The proposed PPF method has a simulated input impedance of 150Ω in-parallel with 18fF.