Highly Tunable Integrated Self-Interference Cancellation Techniques for Intelligent Full-duplex Radios

Abstract

The growing demand for wireless connectivity in both defense and commercial applications, such as autonomous vehicles, smart cities, industrial IoT, and augmented reality (AR) / virtual reality (VR), continues to drive research towards increasing date rates in mobile transceivers while simultaneously reducing power consumption, form factor, and costs.With the advent of fifth generation (5G) and the ongoing development of sixth generation (6G) technologies, the increased utilization of the limited wireless spectrum, particularly in the S and C bands, for higher bandwidth and data rates has posed significant interference challenges among transceivers. In-band Full-duplex (FD) communication offers a solution by increasing spectral efficiency by enabling a radio's transmitter and receiver to operate simultaneously on the same channel frequency. This capability is particularly valuable for 5G/6G applications that require high data rates in congested wireless networks. However, a major challenge in FD systems is self-interference (SI), where the radio's transmitter signal interferes with its own receiver, degrading the radio's performance. This dissertation explores and implements integrated FD radio front-end solutions designed to mitigate SI and enhance data rates. The research focuses on developing SI cancellation techniques with high tunability, broad cancellation bandwidth, deep cancellation depth, and fast configuration speed. These innovations aim to enable practical radio hardware solutions for true FD operation, addressing the challenges of wireless network congestion in 5G/6G communications. This dissertation begins with a theoretical analysis of the design considerations for a feedfordward canceler for broadband SI cancellation, supported by circuit simulation and measurement results. A testbed including an integrated electrical balanced duplexer (EBD) coupled with a finite impulse response (FIR) filter-based feedforward canceler is used to evaluate the efficacy of the proposed design guidelines. Next, a linearity model is developed to examine the generation of nonlinearties from common- and differential-mode SI at the input of FD radio receivers, providing a strategy to minimize SI-induced distortion from nonlinear receiver impedance. These design considerations are then applied to the implementation of two FD transceiver front-end integrated circuits (ICs) featuring SI cancellation capabilities. The first IC is a FD transceiver front-end designed to achieve broadband SI suppression, with cancelers calibrated for enhanced linearity and the ability to cancel long-delay spread SI. Fabricated in a TSMC 40 nm CMOS process, this chip integrates an EBD with a tuned impedance matching network (Z\textsubscript{Bal}), two broadband complex 5-tap continuous-time FIR-based RF cancellation filters, and a mixed-signal baseband cancellation path operating with a Xilinx RFSoC to address long-delay spread ($\tau$$=$+174 \textit{n}s) SI. This design achieves a measured SI suppression of 62 dB across a +120 MHz bandwidth for delay spreads between 0-0.28 \textit{n}s, and SI cancellation of 23 dB across +120 MHz bandwidth for delay spreads between 0.4-174 \textit{n}s. The RF canceler, calibrated using digitally-controlled current DACs, demonstrates a maximum input-referred third-order intercept point (IIP\textsubscript{3}) of +42 dBm. The receiver has a measured noise figure of 6.8 dB and an IIP\textsubscript{3} of -21 dBm at the maximum gain setting of 40 dB. Additionally, an integrated harmonic-rejection power amplifier (PA) achieves a measured maximum output power (\textit{P\textsubscript{Sat}}) of 19.1 dBm and power-added efficiency (PAE) of 27\%. The second IC demonstrates a highly tunable SI canceler augmented with a machine-learning-based adaptation loop for deep cancellation, enhanced linearity, and accelerated convergence time. This prototype 2.4 GHz canceler chip, fabricated in a 40 nm CMOS process, features extensive tuning capabilities in filter coefficients, delay spread, and linearity. It operates in concert with a neural network (NN) algorithm implemented on a Xilinx RFSoC evaluation kit to optimize the canceler's adaptation process. Designed as a discrete add-on, this canceler IC can be integrated with transceiver chips from different manufacturers. The chip, implemented as a 6-complex tap finite impulse response filter, achieves a measured maximum SI cancellation of 32 dB over a 40 MHz bandwidth and an IIP\textsubscript{3} of +38 dBm. The proposed NN computes the initial settings for the canceler, followed by a local optimization process, achieving a convergence time of about 10 miliseconds in real-world wireless environments. The combined techniques proposed in this dissertation, focusing on enhancing tunability of SI cancellation, demonstrate a potential to achieve deeper cancellation depth, broader cancellation bandwidth, higher canceler linearity, and faster adaptation convergence for FD radios. These advancements enable new opportunities to increase wireless network capacity, addressing the growing demands of future 6G applications.