FPGA Development of an Emulator of the RD53A Prototype Chip and its Integration with Various Readout Systems

Abstract

In 2024 the Large Hadron Collider will be shut down for a major upgrade of the particle detectors and collider systems that will increase the number of collisions occurring in the LHC. As part of this upgrade the front-end particle detectors will be replaced with the RD53 chip [6], which combines the analog pixels which detect the particles with digital control, data processing, and readout systems that control the chips behavior. The RD53 project has released a prototype version of the chip, the RD53A, and has begun the process of designing its successor, the RD53B. As part of the upgrade new readout systems are being designed that can handle the new data rates as well as communicating with the RD53A. To assist with these efforts, the Adaptive Computing Machines and Emulators (ACME) lab has designed an FPGA based emulator of the chip in Verilog. The emulator is built to produce realistic hit data and can be used as a substitute for the real RD53A chip for testing/debugging purposes. More recently work has been done on the emulator to make it compatible with several of the prominent readout systems being developed for the coming upgrade. These include YARR [8], RCE [9], and FELIX [10]. The necessary background, the current state of the emulator, and the work done on it regarding the listed readout systems are discussed in this thesis.