FPGA Design Upgrades for the ATLAS Pixel Readout System in the Large Hadron Collider

Abstract

The ATLAS Pixel Detector in the Large Hadron Collider uses a system of FPGAs in the off-detector readout system. The Read Out Driver (ROD) is a major component of the system that handles processing of front end data and sending it to the next stages of filtering and storage. This thesis starts with a background on the detector and readout system and moves on to discuss efforts in support and development of ROD firmware. The first project investigated anomalous behavior in the ROD Histogrammer. This was understood and resolved after testing in the SR1 facility, which has a mockup of the detector hardware. The second project, called Smart L1A Forwarding, was restarted in 2022 with an objective to mitigate desynchronization of data in Pixel during the challenging conditions of Run-3. Initial development and tests in SR1 and the detector have shown promising results. Further modifications have been made in an attempt to resolve issues found during testing; these modifications are being tested in the detector.