Development of a High-Speed Hit Decoder for the RD53B Chip

Abstract

The Large Hadron Collider (LHC) is undergoing an upgrade, called the High Luminosity LHC (HL-LHC), that will increase the data rates produced by particle collisions by tenfold from what they currently are. ATLAS and CMS experiment sites are designing the next generation read out chips named RD53 to be able to handle the increase in data rates. To accomplish the task, an encoding system was implemented in the second trial of chip development known as the RD53B to help shrink data streams and reduce the overall bandwidth of the system. An exploratory effort was undertaken to create a hardware decoder for Field Programmable Gate Arrays (FPGA) to cut down on CPU usage from software decoders later in the system. A parallelized hardware decoder was designed to meet the data rates produced by an RD53B chip. Overall, the final product is a base hardware decoder design that can handle the throughput constraints of a single RD53B and is resource efficient. The necessary background, hardware decoder design, and the decisions made throughout the process will be outlined in this thesis.