Exploiting Co-Design & Computation for Energy-efficient Systems On Chip

Abstract

System-on-Chips (SoC) are the engines of modern computing. Unfortunately, with the plateauing of performance and energy efficiency benefits provided by each new process technology, power dissipation has become an overriding concern in computing. As an increasing proportion of worldwide energy resources continue to be devoted to high-performance computing (HPC), cloud computing, and pervasive mobile computing, energy efficient SoC design plays a key role thwarting an imminent resource crisis. In SoCs today, voltage margins due to supply noise or PVT variations are a dominant source of inefficiency. This dissertation describes research into two new approaches to address this challenge (1) clocking/voltage co-design and (2) exploiting advances in computing in service of more energy efficient SoC design. Both techniques directly address the problem of SoC voltage margins, the dominant source of inefficiency in CMOS-based computing. It is expected that continued advances in this field will enhance both the effectiveness and applicability of these design approaches. The key idea behind clocking/voltage co-design is to unify traditionally independent clock and voltage regulation loops and thus minimize guardband requirements for supply noise and temperature variations. This thesis presents two versions of unified clock and power (UniCaP) architecture. For the first UniCaP work, the rationale for combining voltage and clock regulation loops into a single loop is discussed. This joint loop uses the supply voltage of the domain (Vdd) as the control variable to adjust the operating clock frequency (fclk) and thus lock system clock to REFCLK in order to drastically reduce voltage guardbands while providing performance guarantees. The (UniCaP) architecture is deployed on a 65nm buck-converter based test-chip, demonstrating temperature margin reductions of 40-55mV and 82% average Vdd guardband reduction across 0.6-1.0V without any performance loss from adaptive clocking. While the first UniCaP prototype has demonstrated aggressive margin recovery while regulating average system performance, slow recovery of Vdd droop due to loop dynamics and control techniques in UniCaP has limited its applicability in certain applications requiring performance guarantees in sub-20µs time frames. UniCaP-2, a dual-loop phase-locked adaptive clocking architecture was then proposed to reduce peak cycle loss (ΔΦmax) and cycle-loss recovery time (Trecovery) while enabling higher Vdd margin reduction. Measurements on a 65nm test chip demonstrate 91-99% Vdd margin reduction and 38X Trecovery improvement over first UniCaP prototype. The thesis also quantifies the impact of clock distribution delay (τdist) and Vdd sensitivity on Vdd margin reduction, an open and critical question surrounding adaptive clocking techniques. Because supply voltage Vdd plays a dominant role in determining energy dissipation, Vdd scaling remains the salient approach to energy efficient CMOS computing. Integrated Voltage Regulation (IVR) -- enabling components of an SoC to be partitioned into multiple Vdd domains, each regulated by an on-chip voltage regulator -- dramatically enhances the effectiveness and applicability of voltage scaling. Fast and stable voltage regulator transient response helps minimize Vdd margins required to withstand load current transients that are common in digital systems. This dissertation discusses how computation can be exploited to achieve improved voltage regulation. Computational regulation is presented on different VR modalities to enhance transient performance. The concept is first demonstrated in a Digital LDO and relies on an accurate time-domain model, using low-latency computation to evaluate the state equations at run time for a rapid response. Measurement results from a 65nm CMOS test chip demonstrate a 2.9-cycle mean settling time for processor load variations. Using this fundamental concept, a novel digital control architecture, low-complexity and low-latency Model Predictive Control (MPC), is deployed in integrated voltage regulators (IVRs). Control and datapath optimizations, combined with the advances in computational speed in modern CMOS technology nodes, are key enablers for realizing an IVR buck with optimal transient response. The proposed MPC-buck architecture was implemented in 65nm CMOS. The test-chip achieves a measured 2.49X settling-time (Tsettle) improvement over an optimally tuned Proportional Integral Differential (PID) controller. Typical VR designs include large stability margins to ensure stable response even in worst case scenarios, resulting in overly conservative designs that degrade VR response time. Two methods are presented in this thesis to handle the worst-case stability margining issue. First, Autonomous Gain Tracking (AGT), a low-overhead, low-complexity technique for run-time loop gain adaptation is introduced to the computational LDO. The main idea is to track variations in loop gain by examining 1-bit statistics of the output voltage. Measurement results indicate that AGT successfully performs the broad gain adjustments required for consistently fast transient responses across varying Vin, Vdd, and temperature conditions. AGT is built upon the characteristics of computation LDO response so it cannot be directly applied to other controller designs. The operation of AGT will also be impacted by engineered current waveforms that break the assumption of random Iload noise. To address the limitations of AGT method, the thesis proposes to utilize a pseudo-random binary sequence (PRBS) based approach to excite the dynamics of a feedback loop and automatically adjust loop gain based on the cross-correlation between the injected PRBS noise signal and control output. Calculating the cross-correlation enables identification of the closed-loop impulse response and hence adjustment of control parameters accordingly.