A Study of Synchronous and Asynchronous Circuits in Monolithic 3D Integration

Abstract

Monolithic three-dimensional integration (M3D) has emerged as a promising pathway for extending integrated-circuit scalability beyond conventional two-dimensional (2D) technology. By sequentially stacking active device layers and connecting them through fine-grained metal interlayer vias (MIVs), M3D can improve device density, reduce interconnect length, and enhance energy efficiency. This thesis investigates M3D from both application-driven and layout-methodology perspectives. While M3D offers density and interconnect benefits, its sequential fabrication and vertical stacking introduce reliability concerns related to process variation, thermal effects, and timing uncertainty. To address these challenges, we first studied the quasi delay insensitive asynchronous circuits based on Null Conventional Logic (NCL). The asynchronous circuits address these challenges by eliminating the global clock and using local handshaking, making them robust to timing variations. To explore the complementary benefits of M3D and QDI design, this work proposes a transistor-level M3D methodology for static NCL threshold gates. Results show that M3D-NCL substantially reduces area while improving delay and power over 2D implementations. The second part studies the MIV placement opportunities and design consideration which affect the area, delay, skew, and power of M3D standard-cell designs. A methodology is proposed to study and compare conventional 2D and M3D standard cells in terms of power, performance, and area (PPA). Using this methodology, standard cells are implemented in both 2D and M3D, with different MIV placement strategies considered for the M3D case. Results show that the proposed designs achieve large area reduction with favorable delay, skew, and power trends.