Design Techniques for Pin-Efficient Multi-Level Wireline Transceivers

Abstract

The demand for higher bandwidth links in high performance computing systems, particularly with the advent of chiplet-based and multi-chip module (MCM) architectures, has raised the critical challenge of interconnect bottlenecks. The finite number of available physical I/O pins limits system-level bandwidth, thereby requiring innovative pin-efficient transceiver solutions. This dissertation presents a comprehensive exploration of novel multi-level signaling methods and advanced circuit techniques aimed at designing high-speed wireline transceivers that overcome these limitations.A 12-bit 8-wire 8-level permutation coding scheme is first introduced for parallel wireline transceivers. This scheme achieves a 150\% pin efficiency, significantly reducing the required baud rate for a given data rate, which in turn mitigates inter-symbol interference (ISI). Furthermore, its inherent design suppresses simultaneous switching noise (SSN), electromagnetic interference (EMI), and common-mode noise (CMN). Secondly, a novel non-uniformly quantized successive approximation register analog-to-digital converter (SAR ADC) with code-dependent weights (NUSA-CDW) is proposed for wireline receivers. This ADC architecture offers flexibility in realizing non-linear transfer functions to improve bit-error-rate (BER) compared to conventional SAR ADCs. Thirdly, Chord-PAM4 (CPAM4) signaling is presented as a pin-efficient and noise-resilient multi-level scheme for parallel links. CPAM4 increases pin efficiency by 50\% compared to conventional differential PAM4 signaling when Chord-PAM4 signals are correlated over 4 wires~(CPAM4-6). It enhances pin efficiency by leveraging both amplitude and spatial domain coding, projecting binary input data onto multi-level signals while maintaining robustness against CMN, SSN, and ISI. Finally, a configurable UCIe/LPDDR4X combo-PHY transceiver is designed and implemented in 28nm CMOS technology. This transceiver supports NRZ, PAM4, and the proposed CPAM4 signaling, providing a universal communication solution for die-to-die links that accommodates both data computing and memory access standards. The transceiver in CPAM4-6 mode provides 150\% pin efficiency and 1.19pJ/b energy efficiency at 21Gb/s data rate.