FPGA Development of an Emulator Framework and a High Speed I/O Core for the ITk Pixel Upgrade

Abstract

The Large Hadron Collider (LHC) is the largest accelerator laboratory in the world and is operated by CERN, an international organization dedicated to nuclear research. It aims to help answer the fundamental questions posed in particle physics. The general-purpose ATLAS detector, located along the LHC ring, will see an Inner Tracker (ITk) upgrade during the LHC Phase II shutdown, replacing the entire tracking system and providing many improvements to the detector technology. A new readout chip is being developed for this upgrade by the RD53 collaboration, code named RD53A. The chip is an intermediary pilot chip, meant to test novel technologies in preparation for the upgrade. The work contained in this thesis describes the Field-Programmable Gate Array (FPGA) based development of a custom Aurora protocol in anticipation of the RD53A chip. Leveraging the infrastructure developed to facilitate hardware tests of the custom Aurora protocol, a cable testing repository was created. The repository allows for preliminary testing of cabling setups and gives the users some understanding of the cable performance.