Automated Analog Layout Methodologies for Mixed-Signal SoC Implementation

Abstract

This dissertation presents automated analog layout methodologies for high-performance mixed-signal SoCs. A template-based generator produces block-specific layouts in minutes, coupled with batch-mode verification for fast optimization. The LEGO methodology builds a process-portable analog standard cell library, where verified fixed-dimension cells can be tiled to form larger systems. Using this approach, two interface designs: Advanced Interface Bus (AIB) and Electronic Integrated Circuit (EIC), demonstrate modularity, tight matching, and rapid integration. These methodologies enable efficient analog layout generation while preserving critical performance and symmetry in complex AMS designs.