Enabling Vector Load and Store Instructions on HammerBlade Architecture

Abstract

Traditionally, computer architecture has been dominated by overly complex instruction sets that created a ''solution" to every problem by adding another instruction. If these complex instructions sets are one side of a coin, the Reduced Instruction Set Computer (RISC)-V architecture is the other. RISC-V processors consist of 47 base instructions. Having such a low amount of instructions is both the biggest strength and the biggest weakness of the new era of RISC-V processors. Currently, there is a remarkable lack of high performance RISC-V processors. The Hammerblade architecture is one of the few. The main difference between Hammerblade and other RISC-V processors is its leveraging of parallel computer architecture as a multi-core system. However, while Hammerblade consists of potentially thousands of cores, it does not perform any data-level parallelism.The primary intent of this thesis is to further understand how to increase the local memory throughput by extending the RISC-V core to include Single Instruction Multiple Data (SIMD) loads and stores. This will add the capability to locally load and store four words of data on top of the existing singular word loads and stores. A single Vanilla RISC-V core can now have the potential of a 4x speedup in loads and stores. This will allow Hammerblade to not only leverage the parallelism of the manycore architecture, but also the data-level parallelism on each individual core.