A 40nm CMOS Single-Ended Switch-Capacitor Harmonic-Rejection Power Amplifier for ZigBee Application

dc.contributor.advisor	Rudell, Jacques C
dc.contributor.author	Huang, Chenxi
dc.date.accessioned	2016-04-06T16:31:08Z
dc.date.available	2016-04-06T16:31:08Z
dc.date.submitted	2016-03
dc.description	Thesis (Master's)--University of Washington, 2016-03
dc.description.abstract	This thesis describes a single-ended switch-capacitor harmonic-rejection power amplifier for the 915 MHz ISM band for ZigBee applications. A multipath feed-forward harmonic-rejection technique is employed to suppress the 2nd/3rd/4th harmonics of the switch-capacitor power amplifier (PA) by 48/17/24 dB, respectively. The measured PA peak drain efficiency is 43% at a peak output power of 8.9dBm with the harmonic-rejection enabled. This PA was implemented in a 40nm TSMC CMOS process with an active area of 180μm×700μm.
dc.embargo.terms	Open Access
dc.format.mimetype	application/pdf
dc.identifier.other	Huang_washington_0250O_15612.pdf
dc.identifier.uri	http://hdl.handle.net/1773/35570
dc.language.iso	en_US
dc.subject	CMOS; Power amplifiers; Switched capacitor circuits; ZigBee
dc.subject.other	Electrical engineering
dc.subject.other	electrical engineering
dc.title	A 40nm CMOS Single-Ended Switch-Capacitor Harmonic-Rejection Power Amplifier for ZigBee Application
dc.type	Thesis

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