Millimeter-Wave Digital Beamforming using Low-Resolution ADCs

Abstract

There is an on-going pursuit to design wireless systems that achieve ever higher data rates for multiple users. Phased-array beamforming receivers (RXs) have been demonstrated to support multi-gigahertz bandwidths across the millimeter-wave spectrum. The digital beamforming (DB) architecture is attractive in that it can support the most beams per antenna element compared to the hybrid and analog architectures. However a DB RX requires an identical set of analog-to-digital converters (ADCs), downconverters, filters and amplifiers per element, which, relative to other beamforming architectures, can significantly increase the system area, power consumption and complexity, and in turn limit the system scalability if conventional circuit topologies are used. This thesis studies the utilization of a dithered and oversampled open-loop 1-bit ADC in a DB RX to reduce the front-end power consumption and complexity while maintaining a high signal bandwidth and preserving the system array gain. A behavioral model of a 1-bit ADC is developed and the impact of dithering 1-bit ADCs in a DB RX is analyzed. The circuit design of an oversampled 1-bit ADC in TSMC 28-nm CMOS is described, along with standalone and system-level measurements of the ADC implemented in a 4-element V-band DB RX. The beamforming system achieves a maximum QPSK symbol bandwidth of 400 MS/s with a per element power and area consumption of 96 mW and 0.18 mm^2, respectively.