Caches for Complex Open Source System-on-Chip Designs

Abstract

This thesis describes the RTL implementation of the cache system in a system-on-chip design that consists of a shared memory multi-core processor and a tiled manycore processor. It explores the physical design space and the microarchitectural features used in implementing such system. This work contains the details of the L2 victim cache between the manycore array and the DRAM controller, and the 8-way set-associative L1 data cache in the RISC-V multi-core processor. It also explains the implementation detail of the classic 5-stage pipelined processor in each manycore tile, related to memory access and floating-point unit extension. Verifying the correctness of the cache system can be a challenging task on its own. This work documents various testing strategies used to uncover and track down the bugs found in the memory subsystem. Such method involves using an open source memory consistency checking software and devising constrained randomized tests. This project is an extension of the open source hardware projects, BaseJump STL, which aims to reduce the amount of time it takes to create a custom chip by creating a library of reusable SystemVerilog modules commonly used in ASIC designs, and BaseJump Manycore, an open source tiled architecture designed for computing efficiency, scalability and generality.