Optimizing FPGA Resource Allocation in SDR Remote Laboratories via Partial Reconfiguration

Abstract

Software-Defined Radio (SDR) remote laboratories provide engineering students in wireless communications and radio frequency courses with hands-on experience using SDRs. These devices are renowned for their flexibility and reconfigurability via software. However, cost-effective SDRs often feature lower-end System-on-Chips (SoCs) with Field Programmable Gate Arrays (FPGAs) capable of parallel data processing but limited in hardware resources for running complex digital signal processing algorithms. This limitation restricts their use to simpler FPGA-based tasks, reducing their operational flexibility. Partial Reconfiguration (PR) offers a compelling solution to these limitations by dynamically allocating hardware resources based on the system’s operational mode, enhancing the FPGA's functionality. PR allows the execution of complex programs by enabling independent modifications, recompilation, and reconfiguration of specific FPGA regions without requiring a full project recompile. This process streamlines modifications, shortens development cycles, and enables rapid iteration, significantly improving conventional FPGA programming techniques. This thesis investigates the implementation of PR within SDRs, specifically on Red Pitaya’s SDR platforms which, to the best of our knowledge, have not been previously used for PR. It also explores the integration of this implementation into the existing structure of an SDR remote laboratory. Experimental results demonstrate notable improvements in hardware efficiency, including reductions in logic resource utilization and total power consumption, compared to traditional FPGA reconfiguration methods. These findings underscore the potential of PR in advancing the field of SDR.