Development of an FPGA emulator for the RD53B chip

Abstract

The world’s largest particle accelerator, called Large Hadron Collider (LHC), will go through a long shutdown (LS) in 2024. Particle detectors and systems will be upgraded in order to increase the particle collision rate. So far, the LHC has been able to complete the standard model of Physics by detection of the Higg’s Bosun, but after the new upgrades it is expected to contribute towards the exploration of new physics. One such upgrade will be seen in the ATLAS detector’s Inner Tracker (ITk), where the entire tracking system will get replaced with improved systems. A second prototype version of a test chip for the new hardware is being developed by the RD53 collaborators, called as RD53B (succeeding the RD53A). The Adaptive Computing Machines and Emulators (ACME) Laboratory at the University of Washington develops and maintains the Field Programmable Gate Array (FPGA) focused emulator of the test chips. The primary reason for this effort is the inadequate availability of the chip to researchers, the inability to generate realistic data, and the time it takes to make any changes to the real system. The emulator resolves all these issues faced by physical chips, as it is in an open source repository, produces realistic data without need of a radiation source, and takes hours instead of months to make changes to the System Verilog code. The necessary background information, emulator design, and work done on it is explained in the thesis.