Automatic measurement-based characterization of off-chip interconnect circuitry using lumped elements

Abstract

As clock speeds of digital circuits continue to increase, the performance of board-level and package-level circuitry has become an important factor in digital design. The same is true in the consumer wireless communications market, in which low-cost designs necessitate the use of low-performance interconnect solutions. In order to consider the effects of interconnect circuitry in the design stage of a circuit or system, interconnections must first be effectively modeled for simulation.Many different interconnect modeling solutions have been proposed and implemented in the history of circuit design. Key issues faced in developing a modeling approach are the compatibility of the model with existing simulation tools, the stability of the model, the passivity of the model, and the ability of the modeling approach extract as simple a model as is acceptable for a given application. Furthermore, as is requisite in any CAD (computer aided design) application, the approach must be reliable and predictable.In this dissertation a robust modeling approach is presented which extracts a lumped-element model from measured time-domain data. The extracted model is in SPICE-netlist format, which ensures compatibility with the large majority of existing industry tools. The model is shown heuristically to be asymptotically stable, and to a certain degree to be absolutely stable. The modeling approach presented includes the ability to reduce the size of the model for use in a frequency range narrower than that from which it was extracted. Extraction examples are given of typical interconnect structures to verify the accuracy and practicality of the approach.