Transformer-Based Tunable Matching Networks implemented in Silicon CMOS
Ravish Suvarna, Apsara
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The growing market for small form-factor, low power wireless communication devices has provided tremendous impetus towards research on multi-mode and multi-standard transceiver designs. A key building block in realizing such a transceiver is a reconfigurable/tunable matching network. In this thesis, two tunable matching networks, designed with the explicit goal of providing large impedance-tunability and low insertion loss, at a fixed resonant frequency have been proposed. The two tunable networks, namely Transformer-plus-L-Match Network (TLMN) and Transformer-plus-Pi-Match Network (TPMN) are fully-integrated and prototype test-chips have been realized in a 40nm bulk CMOS process. The transformer in the two networks provides fixed impedance conversion and switch-capacitance based L/Pi-network provides a variable impedance transformation. A design methodology highlighting the loss mechanism in a transformer-based matching network is presented. Based on this methodology, circuit conditions to obtain minimum insertion loss are derived.
- Electrical engineering