PCAST: A Practical Capacitor Array Synthesizer Targeted for SAR-ADC Implementation

Abstract

In this thesis, we introduce PCAST, a practical capacitor array synthesizer targeted for SAR-ADC implementation developed in the SKILL language, which is natively supported by the Cadence EDA tools. We demonstrate that the proposed tool is capable of performing placement and routing of capacitor array layout under the symmetry and matching constraints. The layout generation is performed in two steps. The first step is generating a metal-oxide-metal (MOM) unit capacitor layout and symbol. The second stage is generating the layout, netlist, and symbol of the capacitor array. The synthesizer supports a wide range of user-specified parameters. The supported users specified parameters are chosen in consultation with experienced circuit designers to ensure the proposed tool can be effectively deployed in production. The output of PCAST is in GDSII format, ensuring the tool can be seamlessly integrated with circuit design software. The correctness of the synthesized layout can be validated by the physical verification tools. For each design, PCAST automatically outputs the capacitance parasitics and the mismatch for SAR-ADC linearity characterization. PCAST has been used in production for several SAR-ADCs that have been fabricated in 180nm, 65nm, 28nm CMOS, as well as 16nm and 14nm finFET. It significantly reduces design efforts and the chance of cockpit error in the layout of the capacitor array.