Accurate and stable reduction of RLC networks using split congurence transformations

Abstract

RLC (resistor, inductor, capacitor) network reduction refers to the formulation of small networks whose port behavior is similar to that of large RLC networks. The motivation for this research is that circuits are switching faster so that layout and package parasitics associated with very large scale integrated (VLSI) circuits become more important and require simulation before fabrication. Parasitic effects are often modeled using lumped linear RLC networks which are extracted from the geometry of the layout and package, but these networks are so large that subsequent simulation is impractical or impossible. As a result, it is necessary to reduce these networks after extraction and before simulation. Several network reduction algorithms have been developed in the last few years, but none exist which guarantee both accuracy and passivity (most guarantee only accuracy). If the reduced networks are not accurate then the results of the simulation will probably be wrong, but if the reduced networks are not passive then the subsequent simulation may not work at all. This thesis presents a set of transformations called Split Congruence Transformations (SCT's) which can be used to accurately reduce a network while preserving passivity. Several examples, including a prototype SPICE-in SPICE-out network reduction tool are given which show the utility of SCT's.