High Linearity Full Duplex System Implemented with Novel Impedance Matching Network

Abstract

This thesis provides a design of a full-duplex (FD) communication system that hurdles in the form of the linearity and bandwidth (BW) by utilizing a feedforward canceler for self-interference (SI) cancellation purpose and a tunable impedance matching network to widen the operational frequency. This work is implemented with the TSMC 45nm CMOS technology. With the aid of a highly-linear impedance matching network, the IIP3 can reach +60dBm with a VSWR of 1.5:1. Additionally, the overall cancellation depth from TX to RX is larger than 60dB.