High Linearity Full Duplex System Implemented with Novel Impedance Matching Network

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dc.contributor.advisorRudell, Jacques
dc.contributor.authorYin, Fucheng
dc.date.accessioned2022-04-19T23:45:07Z
dc.date.available2022-04-19T23:45:07Z
dc.date.issued2022-04-19
dc.date.submitted2021
dc.descriptionThesis (Master's)--University of Washington, 2021
dc.description.abstractThis thesis provides a design of a full-duplex (FD) communication system that hurdles in the form of the linearity and bandwidth (BW) by utilizing a feedforward canceler for self-interference (SI) cancellation purpose and a tunable impedance matching network to widen the operational frequency. This work is implemented with the TSMC 45nm CMOS technology. With the aid of a highly-linear impedance matching network, the IIP3 can reach +60dBm with a VSWR of 1.5:1. Additionally, the overall cancellation depth from TX to RX is larger than 60dB.
dc.embargo.termsOpen Access
dc.format.mimetypeapplication/pdf
dc.identifier.otherYin_washington_0250O_23820.pdf
dc.identifier.urihttp://hdl.handle.net/1773/48500
dc.language.isoen_US
dc.rightsnone
dc.subject
dc.subjectElectrical engineering
dc.subject.otherElectrical engineering
dc.titleHigh Linearity Full Duplex System Implemented with Novel Impedance Matching Network
dc.typeThesis

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